Magnetic recording and reproduction of digital information

ABSTRACT

m bit data words are converted into one or two n bit (n&gt;m) record words wherein the absolute value of a recording current is less than a predetermined value so as to eliminate a DC component from the recording current. Reproduction is made according to a partial response method thus enabling high linear bit density.

BACKGROUND OF THE INVENTION

This invention relates to a method and apparatus for magneticallyrecording and reproducing digital informations, more particularly amethod and apparatus for magnetically recording and reproducing digitalinformations with AC coupled magnetic heads.

A typical example of such apparatus utilizes a rotary head for recordinginformations on a magnetic tape and for reproducing the recordedinformations. This rotary head type recording apparatus is advantageousin that as it is possible to increase the relative speed between thehead and the tape, the reproduced signal can be made large and that whencombined with servo technique it is possible to have a high trackdensity recording. The recording current of this type of recordingapparatus should not contain any DC component because the apparatus isprovided with an AC coupling means in the form of a rotary transformerbetween a write driver and a write head. If a recording currentcontaining a DC component were supplied to the apparatus, the currentpassed through the rotary transformer would be distorted thus not onlycausing errorneous writing but also errorneous read out.

SUMMARY OF THE INVENTION

Accordingly, it is the principal object of this invention to provide amethod and apparatus for magnetically recording and reproducing digitalinformations by using an AC coupled magnetic head at high lineardensity.

Another object of this invention is to provide a method and apparatusfor recording and reproducing digital informations which is free from anerror propagation at the time of reproduction.

In short according to this invention, these and other objects can beaccomplished by converting a m bit data word into a record word which isone of two record words corresponding to the data words and having nbits (n>m), so that the absolute value of the recording current of theconverted record word may be less than a predetermined value, therebyeliminating the DC component in the recording current and enabling ahigh recording density by using a partial response system.

According to one aspect there is provided a method of magneticallyrecording and reproducing digital informations characterized bycomprising the steps of preparing a conversion table in which data wordseach comprising a plurality of (m) bits correspond to respective recordwords each having n bits (n>m) and in which an integrated value of NRZIrecording current becomes zero or correspond to two record words eachincluding n bits and in which the integrated value of the NRZI recordingcurrent is not zero and polarities of the two record words are opposite,partitioning an original information bit sequence into data words atevery m bits, converting the data words into record words when theformer correspond to record words in the conversion table, when one ofthe data words corresponds to two second words in the conversion table,converting one of the record words into a record word such that, inaccordance with the integrated value of the NRZI recording current up toa conversion point, an absolute value of the integrated value woulddecrease, recording a record word sequence obtained by the conversion ona magnetic medium as a magnetic polarity inversion sequence

    a.sub.0,a.sub.1,a.sub.2 . . . a.sub.i . . .

where a_(i) represents by 1 or -1 a magnetic polarity inversion in whichtwo N poles oppose each other or two S poles oppose each other and by Oa magnetic polarity non inversion, and i represents a position in themagnetic polarity inversion sequence, reading the magnetic polarityinversion sequence out of the magnetic medium, converting read outinformations into a 3 valued detected digit sequence of class 1 partialresponse type expressed by

    b.sub.0,b.sub.1,b.sub.2 . . . b.sub.j . . .

where b_(j) =a_(j-1) +a_(j) ; and converting the detected digit sequenceinto an bit data words at every n digits and reproducing the m bit datawords.

According to another aspect of this invention, there is providedapparatus for recording and reproducing digital informations,characterized by comprising an encoder provided with a conversion tableaccording to which m bit data words are converted into n bits (n>m)record words by the data words acting as address inputs, an n bit shiftregister which m parallel stores, at a first timing, the n bit recordwords outputted from the encoder, an NRZI recording current modulatorfor producing a NRZI recording current in accordance with serially readout record words from the shift register at a second timing, a headconnected to receive outputs of the NRZI recording current modulator forrecording digit informations on a recording medium, means for detectingwhether an integrated value of the NRZI recording current is zero ornot, and for generating a control signal which selects a record word tobe converted by the encorder according to a data word supplied at thenext time according to an output of the detecting means and theintegrated value of the NRZI recording current up to a conversion point,the conversion table of the encoder including a first portion in whichrespective data words are converted into one record word wherein theintegrated value of the NRZI recording current becomes zero, and asecond portion in which respective data words are converted into tworecord words wherein the integrated value of the NRZI recording currentis not zero and the record words have different polarities, and thecontrol signal generating means sending to the encoder a control signalwhich selects a record word having a sign which makes small theintegrated value of the NRZI recording current up to a conversion pointwhen the detecting means determines that the integrated value of theNRZI recording current does not become zero.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings

FIG. 1 shows the content of a conversion table showing an encoding ruleand useful to explain embodiments of the method and apparatus formagnetically recording and reproducing digital information according tothis invention;

FIGS. 2a through 2j are waveforms of the recording and reproducingsignals and are useful to explain the operation of the apparatusembodying the invention;

FIG. 3 is a block diagram showing a preferred embodiment of a recordingapparatus embodying the invention;

FIGS. 4a through 4o show waveforms at various portions and are useful toexplain the operation of the apparatus shown in FIG. 3;

FIG. 5 is a block diagram showing preferred embodiment of a reproducingapparatus according to this invention;

FIGS. 6a through 6o are waveforms of various portions and are useful toexpalin the operation of the reproducing apparatus shown in FIG. 5;

FIG. 7 is a block diagram showing a modified recording apparatusembodying the invention; and

FIGS. 8a through 8o show waveforms of various portions and are useful toexplain the operation of the modified recording apparatus shown in FIG.7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing preferred embodiments of this invention reference ismade to FIG. 1 showing a conversion table for explaining rules ofencoding and decoding utilized in this invention. FIG. 1 showscorrespondences among data words, conversion conditions, record words,NRZI recording currents, amplitude detection bits, inversion detectionbits and reproduced data words. The data word to be recorded comprises 3bits (m=3) for preparing 8 digital informations of from "000" to "111,"and the record word to be recorded comprises 4 bits for preparing 10digital informations. Accordingly, each data words corresponds to one ortwo record words. The integrated values (hereinafter called "record wordcharges") of the NRZI recording currents of respective record wordscorresponding to the data words at a 1:1 ratio, that is "1111", "1101","0010", "0111", "0101" and "1010" are respectively zero.

Those wherein one data word corresponds to two record words are recordwords "1110" and "0001" corresponding to the data word "001" and thedata words "1001" and "0110" corresponding to the record word "101". Therecord word charge of one of these paired record words is +2 whereasthat of the other record word is -2. The absolute value of the NRZIrecording current per one bit cell is calculated to "1" and bit "1" isrepresented by inverting the current at the fore edge of a bit cell. TheNRZI recording current shows a case wherein a recording currentimmediately preceding the record word is positive (shown by a dot), andthe record word charge shows a value of this case. For this reason,where the immediately preceding recording current is negative thepolarity of the NRZI recording current would be inversed. However, evenin such a case, the absolute values of the paired record word chargesare equal and still maintain a relation of opposite polarities.

Where an original information bit sequence comprising only one data wordcorresponding to one record word, the integrated values of the recordcurrents become zero at the ends of respective record words. Where adate word corresponding to two record words appears in the originalinformation bit sequence, the integrated value of the recording currentduring an interval of from the fore end of a leading record word to theaft end thereof becomes +2 or -2. When a data word corresponding to twosucceeding record words is converted into a record word whose recordword charge becomes opposite sign, i.e. -2 (or +2) the integrated valueof a recording current during an interval of from the fore end of aleading record word to the aft end of the record word produced byconverting the data word returns again to zero. The conversionconditions shown in FIG. 1 follow the rule which returns the integratedvalue of the recording current to zero.

A symbol P represents the polarity of a recording current immediatelybefore the record word, and if P were positive it is expressed as "0"whereas it negative as "1". Reference letter C represents "1" when theintegrated value of the recording current during an interval of from thefore end of the leading record word to the aft end of a record wordimmediately preceeding a record word to be converted is larger thanzero, whereas "0" when the integrated value is negative. FIGS. 2athrough 2j show recording and reproducing signals when the data word is"010". The data word "010" shown in FIG. 2a is converted into a recordword "1101" shown in FIG. 2b according to the conversion table shown inFIG. 1. This recording current is encoded by NRZI into a NRZI recordingcurrent shown in FIG. 2c. More particularly, the polarity of therecording current is inverted by bit "1" of the record word. When therecording current flows through the write head, the information isrecorded on a recording medium as a magnetic polarity inversion sequenceas shown. A signal produced by reading a magnetic polarity inversionwith a read head is shown in FIG. 2e as a reproduced pulse. This pulseis equalized into a class I partial response signal utilized in thefield of data transmission. This equalized signal is shown in FIG. 2f asan equalized reproduced pulse. The amplitude values obtained by samplingthe equalized reproduced pulse with a bit spacing T of a record wordhave a constant value A before and after the peak of the equalizedreproduced pulse, and zero at points other than the peak. The equalizedreproduced signal obtained by reading the magnetic polarity inversionsequence and shown by FIG. 2g is obtained as a superimposed signal onthe equalized reproduced pulse corresponding to each magnetic polarityinversion. An intersymbol interference occuring in this case is limitedto that between an information point at an amplitude of +A or -A of anequalized reproduced pulse prior to the equalized reproduced pulsebecomes continuous and the information point at an amplitude of -A or +Aof the equalized reproduced pulse after a point at which the equalizedreproduced pulse became continuous. In this manner, use of the partialresponse system enables to decrease the magnetic polarity inversionspacing even when a relatively large intersymbol interference occursthereby increasing the linear bit density.

When the absolute value of the sampled value of the equalized reproducedsignal is larger than a constant value, for example A/2, the equalizedreproduced signal is converted into "1" whereas when the absolute valueis smaller than the constant value, the equalized reproduced signal isconverted into "0" to obtain amplitude detection bit as shown in FIG.2h. On the other hand, when the amplitude detection bit corresponding toa given inversion detection bit and the amplitude detection bit justbefore the given inversion detection bit are both "1" or when thepolarities of their sampled values are different, the equalizedreproduced signal is converted into "1" whereas in the other casesconverted into "0" to obtain other an inversion detection bit as shownin FIG. 2i.

A combination of an amplitude detection bit and an inversion detectionbit is equivalent to a three valued digit sequence

    b.sub.0,b.sub.1,b.sub.2 . . .

obtained by converting a magnetic polarity inversion sequence.

    a.sub.0,a.sub.1,a.sub.2 . . .

where a_(i) represents by 1 or -1 a magnetic polarity inversion in whichtwo N poles oppose each other or two S poles oppose each other and by"0" magnetic polarity non invertion, and i represents a position in themagnetic polarity inversion sequence. And

    b.sub.j =a.sub.j-1 a.sub.1

FIG. 1 also shows amplitude detection bits and inversion detection bitsobtained in the same manner. A symbol X in FIG. 1 shows that a bitbecomes "0" or "1" according to a previous state. A data word is decodedfrom an amplitude detection bit and an inversion detection bit but inthis embodiment the data word and the record word are related such thatthe second to the fourth bit of the amplitude detection bits form a datawords. When the fourth bit of the inversion detection bits is "1", thefourth bit of the amplitude detection bits is changed to "0". In otherwords, the last bit of the data word is made to "0". Consequently, adata word "010" shown in FIG. 2_(j) is reproduced from the informationshown in FIGS. 2h and 2i.

FIG. 3 illustrates a construction of a recording apparatus utilized tocarry out the recording and reproducing method of this invention. Therecording apparatus shown in FIG. 3 comprises a buffer 11 whichtemporarily stores an inputted data words (in this example 3 bitconstruction) according to a clock pulse CP1 supplied from a timingpulse generator 12, and an encoder 13 which converts the data wordoutputted from the buffer 11 into a recording word according to theconversion table shown in FIG. 1 for the purpose of recording the dataword on a magnetic recording medium, for example a magnetic tape. Theencoder 13 includes a read only memory device ROM 13a which is connectedto receive the output of the buffer 11 comprising a lower order addressbit and the output of an exclusive-OR gate circuit 13b, which comprisesthe most significant bit for producing an output converted into a recordword. The input and output conditions of the ROM follow the conversiontable shown in FIG. 1 and the ROM contains a conversion table as shownin the following Table I, for example. The first bit, i.e., the mostsignificant bit of the ROM addresses shown in Table I is determined bythe output of the exclusive-OR gate circuit, while the second to fourthbits represent a data word supplied from the buffer 11.

                  TABLE I                                                         ______________________________________                                        ROM input address ROM output                                                  decimal       binary  (record word)                                           ______________________________________                                        0             0000    1111                                                    1             0001    0001                                                    2             0010    1101                                                    3             0011    0010                                                    4             0100    0111                                                    5             0101    0110                                                    6             0110    0101                                                    7             0111    1010                                                    8             1000    1111                                                    9             1001    1110                                                    10            1010    1101                                                    11            1011    0010                                                    12            1100    0111                                                    13            1101    1001                                                    14            1110    0101                                                    15            1111    1010                                                    ______________________________________                                    

The output P of a parity calculator 17 and the output C of a chargecalculator 18 to be described later are applied to the inputs of theexclusive-OR gate circuit 13b.

As can be noted from the conversion table shown in FIG. 1, the output ofthe encoder 13 is made up of 4 bits which are applied in parallel toshift register 15.

The encoder 13 is provided for the purpose of converting a data wordinto a record word when the DC component of the NRZI recording currentis to be eliminated, and for selecting one of two record words, thepolarities of the record word charges being different, such that theintegrated value (charge) of the NRZI recording current would be lessthan a definite positive or negative value. As will be described later,the parity calculator 18 is used to check whether the NRZI recordingcurrent of a record word begins from positive or negative value. Withthis measure it is possible to convert data of any pattern into alimited recording current waveform. The shift register 15 has a 4 bitconstruction and is supplied with a preset pulse PP, a clock pulse CP2,and a clear pulse CL from a timing pulse generator 12 to change itscontent. The shift registes 15 sends out serially its content under thecontrol of the clock pulse CP2, and the output of the shift register 15is applied to the parity calculator 17 and the charge calculator 18. Theparity calculator 17 calculates the parity during an interval of theforemost bit of the leading record word and a bit now being inputted soas to calculate the polarity of the recording current. In the case of anodd numbered parity, an output P of "1" is sent to the encoder 13, whilein the case of an even numbered parity an output "0" is applied to theencoder. In this example, the parity calculator 17 is constituted by aJ-K master-slave flip-flop circuit 17a which when supplied with theclear pulse CL resets to produce a Q output of "0" whereas when suppliedwith the clock pulse CP2 changes its state when the output of the shiftregister 15 is "1" but does not change its state when the output of theshift register 15 is "0". The charge calculator 18 is constituted by aJ-K master-slave flip-flop circuit 18a, 4 bit up-down counter 18b andAND gate circuits 18c and 18d. The charge calculator 18 calculates theintegrated value of the recording current by alternately enabling anddisabling AND gate circuits 18b and 18c under the control of the clockpulse CP3 when a bit "1" is inputted from the leading bit of the firstrecord word so as to switch the operation between count up and countdown and by counting the number of the input bits with the counter 18d.When the integrated value is larger than zero the charge calculatorapplies its "0" output to the encoder 13 whereas an "1" output to theencoder 13 when the integrated value is negative. When supplied with theclear signal CL, the flip-flop circuit 18a and the flip-flop circuit 18dare reset.

The NRZI modulator 16 converts the bits of an inputted record word intoa NRZI recoring current which is sent to a recording head 20 via arotary transformer 19. The NRZI modulator 16 converts a bit "1" of therecord word to an inverted NRZI recording current and converts a bit "0"of the record word into a noninverted NRZI recording current andoperates to decrease the spacing between detected digits which undergointerference when combined with a partial response. With this modulator,the bit "1" is recorded on the recording medium as the magnetic polarityinversion. Accordingly, a reproduced pulse is produced at a bit "1", andthis reproduced pulse is read as (+1, +1) (clase 1 partial response).One bit on the recording side becomes two continuous bits on thereproducing side. Thus, a detected digit interferred by an adjacentrecord bit is only one adjacent bit.

Heretofore an NRZ modulator has been used to provide a class 4 partialresponse (interleaved NRZI). According to this modulator, since therecorded bit "1" is read as a detected digit "(1,0,-1)" the detecteddigits that result in an interference are adjacent two bits. In theprior system, for the purpose of avoiding error propagation a m/nconversion was used. According to this invertion n=m+1, but according tothe class 4 partial response n=m+2. As a consequence, the system of thisinvention has a higher conversion efficiency, i.e., a higher linear bitdensity.

By rotating the rotary head at a high speed, the rotary transformer 19increases the relative speed of the head and the recording medium, forexample larger than 20 m/s (in the case of a stationary head 5 m/s),thus making easy the positioning of the tape and the head by usingsuitable servo technique. In this case, it is necessary to record apositioning signal on the tape. This increases the reproduced signal,the SNR ratio, the linear bit density and the track density.

The operation of the recording apparatus shown in FIG. 3 will now bedescribed with reference to the waveforms shown in FIGS. 4a through 4o.

A clear pulse CL (FIG. 4a) produced by the timing pulse generator 12 attime t₁ clears the shift register 15, the flip-flop circuit 17a of theparity calculator 17, and the flip-flop circuit 18a and up-down counter18d of the charge calculator 18, thus setting an initial state. Underthese conditions contents of the shift register 15 are all zero and theoutputs P and C or the parity calculator 17 and the charge calculator 18are both "0". Then, when a clock pulse CP1 is produced by the pulsegenerator 12 at time t₂ as shown in FIG. 4b a three bit data word, forexample "001" is written into the buffer 11. Thereafter, the buffer 11sends its content to the encoder 13 as shown in FIG. 4c. The encoder 13utilizes this buffer output as a lower address bit of the read outaddress. At this time the parity calculator 17 and the charge calculator18 still keeps their initial states and their outputs P and C are "0" .As a consequence, the output of the exclusive-OR gate circuit 17binputted with these outputs is also "0".

Accordingly, the address designation input to the ROM is "0001" (seeFIG. 4d) and when the address of this ROM is designated, "0001" would beoutputted as the ROM output, that is a record word (see FIG. 4e)according to Table I.

At this time since the shift register 15 produces a "0" output, thestates of the parity calculator 17, the charge calculator 18 and theNRZI modulator 16 do not change.

At time t₃, as shown in FIG. 4f, the timing pulse generator 12 producesa preset pulse PP. When supplied with this preset pulse PP, the shiftregister 15 stores the record word sent from the encoder 13 in parallel.Then the contents of the shift register 15 which have been stored underthe control of a clock pulse CP2 shown in FIG. 2g are sequentially readout.

At time t₃, the clock pulse CP2 is not generated by the timing pulsegenerator 12. Accordingly, the output "0" of the most significant bit ofthe shift register 15 is sent to the parity calculator 17, the chargecalculator 18 and the NRZI modulator 16. Since this output is the sameas the initial state, the states of the most of the elements do notchange. However, as the AND gate circuit 18b is enabled by the Q output"1" of the flip-flop circuit 18a it sends to the counter 18d a clockpulse CP3 as a count down pulse (see FIG. 4l) each time the clock pulseCP3 is generated at time t₄, thus causing the counter 18d to count down.The content of the counter 18d is shown in FIG. 4m. As shown in FIG. 4n,the most significant bit of the counter 18d becomes "1" thereby changingits output C to "1" from "0".

At this time, since the flip-flop circuit 17a of the parity calculator17 is inputted with "0", its output P is still "0". As a consequence,output "1" is sent out from the exclusive-OR gate circuit 13b of theencoder 13. (see FIG. 4o)

At time t₅ the timing pulse generator 12 produces a clock pulse CP2 asshown in FIG. 4g. In response to this clock pulse, the content of theshift register 15 is shifted by one bit toward the output side.Succeeding output of the shift register 15 is "0" which is the same asthat before "0". Thus, the inputs to the flip-flop circuits 17a and 18brespectively of the parity calculator 17 and the charge calculator 18are "0" and when a clock pulse CP3 i.e. applied at time t₃ their statesdo not change. However, since the AND gate circuit 18b is still beingapplied with the Q output of the flip-flop circuit when it is suppliedwith the clock pulse CP3, the AND gate circuit 18b sends again a countdown pulse to the counter 18d. As a consequence, the count of thecounter 18d is counted down by 1 to change its content to -2.

The operations when the timing pulse generator 12 produces clock pulseCP2 and CP3 at times t₇ and t₈ respectively are similar to those whenthe clock pulses CP2 and CP3 are generated at times t₅ and t₆respectively. When supplied with a count down pulse, the up-down counterchanges its content to -3.

Upon generation of a clock pulse CP2 at time t₉, the content of theshift register 15 is shifted as that the least signiciant bit, that is"1" of the content of a data word is sent out as the output of the shiftregister 15.

The NRZI modulator 16 sequentially converts the record word "0001"supplied from the shift register into "0"0"0"1" and sends the convertedsignal to the head 20 via the rotary transformer 19. It is hereinassumed that the initial state of the recording current is "1". (seeNRZI recording current shown in FIG. 6)

When a clock pulse CP3 is generated at time t₁₀, the states of theflip-flop circuits 17a and 18a respectively of the parity calculator 17and the charge calculator 18 are changed to change the Q output to "1"from "0" (see FIG. 4_(j)). As a consequence the output P of the paritycalculator 18 becomes "1". As a result of change of the state of theflip-flop circuit 18a of the charge calculator 18 when a Q output isproduced, the AND gate circuit 18b would be disabled which has beenenabled by the clockpulse CP3, and the AND gate circuit 18c sends out acount up pulse shown in FIG. 4k when it receives the clock pulse CP3with the result that the content of the counter 18d is changed to -2from -3. However, since the most significant bit of this counter isstill maintained at "1" its output C does not change and remains at "1"as shown in FIG. 4h.

Under these conditions since either one of the outputs P anc C is "1"the exclusive-OR gate circuit 13 sends an output "0" as shown in FIG.4o.

At time t₁₂, the clock pulse CP1 is produced again to store the nextdata word "010" in the buffer 11. At this time, since the exclusive-ORgate circuit 13b does not send out "1" as the most significant bit (seeFIG. 14o) "0010" will be applied as an input to the ROM 13a.Accordingly, the ROM 13a sends "1101" (see FIG. 4e) as the record wordto the shift register 15 according to Table I.

The shift register 15 accepts the output of ROM 13a when a preset pulsePP is applied at time t₁₃. At this time, "1" appears at the mostsignificant bit that is the output terminal of the shift register 15(see FIG. 4h). As a consequence the flip-flop circuits 17a and 18b ofthe parity calculator 17 and the charge calculator 18 operate asfollows. Remember that the last bit of the previous data word is "1".This sets the flip-flop circuits 17a and 18a to change their Q outputsto "1". Under these states, when signal "1" is applied again to theflip-flop circuits they are reset to change their Q output to "0"; withthe result that the output P of the parity calculator 17 becomes "0". Atthe same time, the output C of the charge calculator 18 becomes "0" andthe Q outputs of the flip-flop circuits 17a and 18a become "1" so thatthe AND gate circuit 18b is enabled when it receives the clock pulse CP3to supply a count down pulse (see FIG. 4l) to the counter 18d to changeits count -2 to -3. At this time, since the most significant bit of thecounter 18d is still "1", the output C of the charge calculator 18 is"1".

Then when a clock pulse CP2 is supplied to the shift register 15 at timet₂₀ the content thereof is shifted by one bit toward the mostsignificant bit to produce an output "1" at the output terminal.

As a consequence, upon receival of a next clock pulse CP3, the flip-flopcircuit 17a of the parity calculator 17 is set to produce an output C of"1". At the same time, the flip-flop circuit 18a of the chargecalculator 18 produces a Q output of "1", and when the clock pulse CP3is supplied, the AND gate circuit 18c is enabled to send out a count uppulse (see FIG. 4k). Thus, the count of the counter 18d is changed to -2from -3.

Furthermore, when the clock pulse CP2 is applied to the shift register15 at time t₂₁, the content thereof is shifted again by one bit towardthe most significant bit to produce an output "0" at the output terminal(see FIG. 4h).

At this time, even when the clock pulse CP3 is applied, states of theflip-flop circuits 17a and 18a respectively of the parity calculator 17and the charge calculator 18 do not change and continue to send out Qoutput of "1" as shown in FIG. 4j. As a consequence, the paritycalculator 17 continues to produce output P of "1" and the counter 18dof the charge calculator 18 changes its count from -2 to -1 uponreceival of a count up pulse produced by the AND gate circuit 18c.

Thereafter, the parity calculator 17, the charge calculator 18 and theencoder 13 operate sequentially according to the output of the shiftregister 15.

When supplied with a record word "1101", the NRZI modulator 16 suppliesa NRZI recording current of "0110" to the head 20 via the rotarytransformer 19, whereas when supplied with a next record word "1101" themodulator 16 supplies a NRZI current "1110" to the head 20 which inresponse to this current sequentially magnetizes predetermined portionsof the magnetic tape.

FIG. 5 shows the construction of a reproducing apparatus utilized in therecording and reproducing system according to this invention, whichcomprises a reproducing head 31, a rotary transformer 32 connected toreceive the output of the reproducing head 31, an equalizer 33 suppliedwith the output of the rotary transformer 32, an amplitude detector 34supplied with the output of the equalizer 33, an inversion detector 35supplied with the output of the equalizer 33, shift register 36 and 38supplied with the outputs of the amplitude detector 34 and the inversiondetector 35 respectively, a decoder 38 supplied with the paralleloutputs of the shift registers 36 and 37, a buffer 39 supplied with theoutput of the decoder 38 and a timing pulse generator 4o. The equalizer33 equalizes the reproduced pulse such that its sampled values areequalized to a class 1 partial response signal . . . 0, 0, +A, +A, 0, 0. . . . Use of this equalizer permits waveform interference so thatcorrect reading can be assured even with a narrow magnetic polarityinversion spacing, that is with larger linear bit density. The equalizer33 is constituted by a tapped delay line 33a, a resistor 33b connectedbetween one end of the delay line and the ground, variable gainamplifiers 33c-33f connected to the opposite ends of the delay line 33aand intermediate taps, and an adder 33g which adds together the outputsof the amplifiers. Such construction is called a tapped transversalfilter which equalizers the magnitude and polarity of the input signals,i.e., the reproduced pulses to obtain an equalized reproduced pulsewhose waveform is currented. However, detailed description will not bemade herein because its construction is well known. The equalizer shownmay be substituted by an equalizer of the well known construction, forexample utilizing reactance, capacitance and resistors.

The amplitude detector 34 operates to produce a logic signal "1" whenthe absolute value of the sampled value is larger than a predeterminevalue, but a logic signal "0" in other cases. The amplitude detector 34comprises two voltage detectors 34a and 34b, an OR gate circuit 34c, anda 2 bit shift register. Each of the voltage comparators 34a and 34b hasinput terminals A and B, the A input of the comparator 34a and the Binput of the comparator 34b being connected in common to receive theoutput of the equalizer 33. Further, a reference voltage A/2 is appliedto the B input of the comparator 34a, while a reference voltage -A/2 issupplied upon the A input of the comparator 34b. When the voltage of theA input is higher than the voltage of the B input of these comparators,a high level logic output "1" is produced, while in the opposite case alow level logic output "0" is produced. These outputs are supplied to ashift register 34d via an OR gate circuit 34c. The shift register 34dstores the output of OR gate circuit 34c under the timing action of theclock pulse CP11 and the output of the shift register 34d is applied toa series input/parallel output type 4 bit shift register 36. The shiftregister 34d stores its input under the control of the timing pulseCP13.

The inversion detector 35 produces an output "1" when it detects asampled value of opposite polarity whose magnitude is larger than apredetermined value after the detector 35 detects a sampled value havinga magnitude larger than the predetermined value, whereas produced "0" inother cases. The inversion detector 35 comprises a pair of voltagecomparators 35a and 35b, a pair of two bit shift registers 35c and 35d,two AND gate circuits 35e and 35f and an OR gate circuit 35g. Each ofthe comparators 35a and 35b has two inputs A and B, and the A input ofthe comparator 35a and the B input of the comparator 35b are connectedin common to receive the output of the equalizer 33. The B input of thecomparator 35a is supplied with a reference voltage A/2 while the Ainput of the comparator 35b is supplied with a reference voltage -A/2.When the voltage at the A input becomes larger than that at the B inputthese voltage comparators produce outputs "1s", while in the oppositecase outputs "0s". These outputs are serially applied to the shiftregisters 35c and 35d to be sequentially stored therein under thecontrol of the clock pulse CP11. The AND gate circuit 35e is enabledwhen the first bit of the shift register 35c and the second bit of theshift register 35d coincide with each other so as to check whether theinformation has inverted or not. The AND gate circuit 35f is enabledwhen the second bit of the shift register 35c and the first bit of theshift register 35d coincide with each other. The outputs of the AND gatecircuits 35e and 35f are applied to the series input parallel outputtype 4 bit shift register 37 via the OR gate circuit 35g as the outputof the inversion detector 35.

Above described amplitude detector 34 and inversion detector 35 processthree valued informations read with binary logic circuits. According toclass 1 partial response method. The use of these detectors enables touse binary logic circuits, thus making the apparatus small in size anddecreasing the cost.

The shift register 37 stores input data under the control of the clockpulse CP13.

The operation of the reproducing apparatus shown in FIG. 5 will now bedescribed in detail with reference to FIGS. 6a-6o.

Assume now that the data words appear in the order of "001", "01" and"101" as shown in FIG. 6a, then the record words recorded on themagnetic tape are shown in FIG. 6b. Accordingly, as shown in FIG. 6c,the NRZI recording current for recording these record words on themagnetic tape is inverted only at a bit "1".

The reproduced signal picked up by the reproducing head 31 and thenequalized by the equalizer 32 is shown by FIG. 6d. The equalizedreproduced signal is applied to the amplitude detector 34 and to theinversion detector 35. At times t₃₁ and t₃₂ the equalized reproducedsignal is zero so that respective voltage comparators 34a, 34b, 35a and35b do not produce any output. FIGS. 6e and 6d show output waveforms atthe output terminals a and b of the voltage comparators 34a, 35a, 34band 35b. Each of the shift registers 34d, 35c, 35d, 36 and 37 is set tothe initial state by a clear signal CL at the beginning of reproduction.

From time t₃₂, the equalied reproduced signal gradually increases in thepositive direction. At time t₃₃, since the equalized reproduced signalbecomes larger than the reference value A/2 applied to voltagecomparators 34a and 35a, "1s" are sent out from the output terminals aof these comparators 34a and 35a. These outputs are continued until thereproduced signal becomes smaller than A/2 at time t₃₅. This state isshown in FIG. 6e. The "1" output of the voltage comparator 34a is storedin the first bit of the shift register 34d via the OR gate circuit 34cunder the control of the clock pulse CP11 generated at time t₃₄ shown inFIG. 6g, while the output of the voltage comparator 35c is storeddirectly in the shift register 35c at the same time under the control ofthe clock pulse CP11. The "1" informations stored in these shiftregisters 34d and 34e are shifted to the second bits respectively underthe control of the clock pulse CP11 generated at time t₃₆. As aconsequence, an output as shown in FIG. 6h appears on the outputterminal of the shift register 34d and an output as shown in FIG. 6iappears on the output terminal d of the shift register. Under thesestates, the output of the voltage comparator 35b would not be applied toshift register 35d at either one of the times t₃₄ and t₃₅. Consequently,at these times neither one of the AND gate circuit 35e and 35f isenabled.

At time t₃₉ (in this example, this time accidentaly coincides with theprocessing time described above) the equalized reproduced signal passesthrough a zero level and varies in the negative direction until timet₃₇. However, it should be understood that the equalized reproducedsignal changes in a range in which the voltage comparators 34b and 35bdo not produce any output.

The shift register 36 stores the output C of "1" of the shift registers34d under the control of the clock pulse CP11 generated at time t₃₇ andthereafter sequentially shifts this "1" information from the first bittowards the higher order bit each time the clock pulse CP11 is aplied.

At time t₃₈ when the equalized reproduced signal exceeds again referencevalue A/2, the voltage comparators 34a and 35a produce outputs "1" whichare stored respectively in a manner described above, and at time t₄₀these stored signals are produced from the output terminals c and d ofthe shift registers under the control of the clock pulse CP11. Theseoutputs are produced because the equalized reproduced signal crosses alevel A/2 and approaches toward zero at time t₄₁.

The shift register 36 stores the output C of the shift register 34dunder the contrl of clock pulse CP11 consequently the output C of "1"produced at time t₃₆ is stored in the shift register 36 at time t₃₂, andthe shift register 36 produces an output whose first bit is "1" and thesecond and third bits are "0". The shift register 35c of the inversiondetector 35 produces an output d of "1" at a time t₃₆, but at time t₃₇its contents overflows to produce an output d of "0". For this reason attime t₃₇ the output f of the inversion detector 37 is "0" so that "0" isstored in the first bit of the shift register 37. Accordingly, at timet₃₇, the inverter 38b of the decoder 38 supplies an output "1" to theAND gate circuit 38a whereby it is enabled to supply the output "1" tothe buffer 39 which stores the output of the recoder 38 at time t₃₉following time t₃₇ under the control of the clock pulse CP12. At thistime, the output of the AND gate circuit is "1" and the second and thirdbits of the shift register 3o are "0", so that a data word "001" shownin FIG. 6o is stored in the buffer 39, and the stored data word is sentto a succeeding stage as a reproduced data word.

At time t₄₄ since the equalized reproduce signal becomes smaller thanthe reference value A/2, at time t₄₁ the voltage comparators 33a and 35astop to send out outputs "1". At time t₄₂ the equalized reproducedsignal passes through the zero level and then begins to vary in thenegative direction, and at time t₄₃ the equalized reproduces signalpasses through the level of -A/2. At this time the voltage comparators34b and 35b produce "1" outputs at their output terminals b. These "1"outputs are produced until the equalized reproduced signal becomessmaller than -A/2 at t₄₅. It is to be noted that, as can be noted fromthe waveforms shown in FIGS. 6d, 6e, 6f and 6g the outputs a of thevoltage comparators 34a and 35a and the outputs b of the voltagecomparators 34b and 35b are generated with a small time spacing andstored in the succeeding registers by a continual clock pulse CP11.

Consequently, as shown in FIG. 6h output "1" appears at the outputterminal c of the shift register 34a at either one of time t₄₄ and t₄₆.This "1" output is sent to shift register 36 and sequentially stored inthe first bit thereof each time a clock pulse CP11 is generated. Thecontent of the shift register 36, especially the contents of the first,second and third bits ar sent to the decoder 38 where they are decodedand then sent to the buffer 39. However, as shown in FIG. 6h, since thisbuffer stores the output of the decoder 38 under the control of theclock pulse CP12, the variation in the output of the decoder during aninterval in which the clock pulse CP12 is generated has no influenceupon the output side.

At time t₄₀, the shift register 35e stores the output "1" appearing atthe output terminal of the voltage comparator 35a and at time t₄₄ thisinformation "1" is shifted from the first bit to the second bitconnected to the output terminal d. This state is shown in FIG. 6i. Attime t₄₄ the shift register 35d stores the "1" output appearing at theoutput terminal b of the voltage comparator 35b. At this time, an output"1" appears on the output terminal of the shift register 35c. As aconsequence, the AND gate circuit 35f is enabled to produce an output"1" on the output terminal f of the inversion detector 35 via the ORgate circuit 35g (see FIG. 6 k). At time b₄₅, the voltage comparator 35bstops to produce an output. At time t₄₆, the shift registers 36 and 37respectively store the output C of the amplitude detector 34 and theoutput f of the inversion detector 34 under the control of the clockpulse CP11 produced at time t₄₆. Then at time t₄₇ the "1" shiftinformations of the first bits of the shift registers 36 and 37 areshifted to the second bits.

Under this state, the buffer 39 stores an input under the control of theclock pulse CP12 generated at time b₄₈. Since the inputs to the AND gatecircuit 38a of the decoder 38 are "0" and "1", this gate is not enabledso that this AND gate circuit applies its "0" output as the third bitinput of the buffer 39. Further, the second bit of the shift register 36is "1", so that this signal "1" is sent to the buffer 39 as the secondbit input. Since the third bit of the shift register 36 is "0", this "0"information is sent to the buffer 39 as the fourth bit input. As aconsequence, the buffer 39 sends out a data word "010" shown in FIG. 6o.

Thereafter various elements operate in the same manner as abovedescribed to reproduce a data word "101" and succeeding data words aresequentially reproduced. The waveforms shown in FIGS. 6l and 6m showthose of the fourth bits of the shift registers 36 and 37.

FIG. 7 shows a modified recording apparatus in which elements identicalto those shown in FIG. 3 are designated by the same referencecharactors. The recording apparatus shown in FIG. 7 is characterized inthat the encoder 13 and the charge calculator 18 shown in FIG. 3 arecombined into a single processing unit, i.e., an encoder/chargecalculator 51 which is constituted by a read only memory device (ROM)50a, an arithmetic operation unit 50b, a register 50c, an exclusive-ORgate circuit 13b and a D-type edge triggered flip-flop circuit 50d. Likethe ROM 13a shown in FIG. 3, the ROM 50a receives a three bit data wordssent through the buffer 11 as a lower order address and an one bit sentfrom the exclusive-OR gate circuit 13b via the flip-flop circuit 50d asthe most significant bit for producing a 4 bit record word, a one bitparity and a 3 bit record word charge based on these inputs andaccording to the following conversion Table II

                  TABLE II                                                        ______________________________________                                                     ROM output                                                       ROM address    record            record word                                  decimal                                                                              binary      word    parity  charge                                     ______________________________________                                        0      0000        1111    0       000                                        1      0001        0001    1       010(+2)                                    2      0010        1101    1       000                                        3      0011        0010    1       000                                        4      0100        0111    1       000                                        5      0101        0110    0       010(+2)                                    6      0110        0101    0       000                                        7      0111        1010    0       000                                        8      1000        1111    0       000                                        9      1001        1110    1       110(-2)                                    10     1010        1101    1       000                                        11     1011        0010    1       000                                        12     1100        0111    1       000                                        13     1101        1001    0       110(-2)                                    14     1110        0101    0       000                                        15     1111        1010    0       000                                        ______________________________________                                    

The record words are sent to the shift register 15 in the same manner asthe preceeding embodiment, while the parity check information is sent tothe parity calculator 17. The record word charge information is sent tothe arithmetic calculating unit 50b which also receives the output ofthe shift register 50c in addition to the record word chargeinformation. Based on the output P of the parity calculator 17 thearimetic opeation unit (ALU) 50b determines whether the record wordcharge is to be added or subtracted to and from the output of register50c. For example, when the output P is "1", the arithmetric unit becomesan addition mode. On the other hand, when the output is "0," thearithmetic unit becomes the subtraction mode.

The result of operation of the arithmetic operation unit 50b is storedin register under the control of the clock pulse CP4. The register 50cis set to the initial state by the clear signal CL. The most significantbit of the register 50c is sent to the exclusive-OR gate circuit 13_(b1)to act as the output C that is the output of the charge calculator. Theoutput P of the parity calculator 17 is also applied to the exclusive-ORgate circuit 13_(b1). Thus, this OR gate circuit, calculates theexclusive-OR logic of the outputs P and C and applies its output to theflip-flop circuit 50d which stores the output of the exclusive-OR gatecircuit 13_(b1) each time a clock pulse CP5 is generated and sends outits output as the most significant bit address designation informationof the ROM 50a. The timing pulse generator 12A utilized in thismodification produces clock pulses CP4 and CP5 in addition to the outputCL, CP1-CP3 and PP which are generated by the timing pulse generator 12shown in FIG. 3.

The operation of this recording apparatus will now be described withreference to the waveforms shown in FIG. 8.

The clear pulse CL (FIG. 8a) generated by the clear pulse CL generatedby the timing pulse generator 12A at a time t₅₁ clears the shiftregister 15, the flip-flop circuit 17a of the parity calculator 17, theregister 50c of the arithmetic operation unit 51 and the flip-flopcircuit 50d and sets these circuit elements to their initial states.Under these states, the contents of the shift register 15 are all zeroand the output P of the parity calculator 17 and the output C of thearithmetic operation unit 51 are both zero.

Then, as shown in FIG. 8b, the clock pulse CP1 is generated at time t₅₂to store a bit 3 data word, for example "001" in the buffer 11.Consequently, thereafter the buffer 11 continues to send its content tothe arithmetic operation unit 51 until the content of the buffer 11 isupdated by the clock pulse CP1 as shown in FIG. 8c. The arithmeticoperation unit 51 utilizes the output of the buffer as a lower orderaddress bit of the read out address of the ROM 50a.

At this time, the parity calculator 17 and the register 50c of thearithmetic operation unit 51 are still maintained in their initialstates and the both outputs P and C are "0". Accordingly, the output ofthe exclusive-OR gate circuit 13_(b1) of the arithmetic operation unit51 supplied with these outputs P and C is "0" and hence the output ofthe flip-flop circuit 50d is also "0".

Consequently, as shown in FIG. 8d the address designation input to theROM 50a becomes "0001" and the address designation of this ROM is madeto be a ROM output of "0001," that is a record word "0001". Then aparity check information of "1" and a record word charge information of"+2(010)" are sent out (see FIG. 8e) according to Table II. The shiftregistor 15 stores in parallel the record word "0001" when the clockpulse PP shown in FIG. 8f is generated. Then the shift register 15sequentially sends to the NRZI modulator 16 its content which has beenstored by the clock pulse CP2 shown in FIG. 8g starting from the mostsignificant bit. FIG. 8h shows the variation of the output sent out fromthe shift register 15.

The NRZI modulator 16 supplies a NRZI recording current of "0001" to thehead 20 via the rotary transformer 19 according to the conversion tableshown in FIG. 1 as the clock pulse CP2 is generated so as to write thisrecord word of "0001" on the magnetic tape.

The +2 (010) record word charge information generated at the time whenROM 51 converts the sign in response to the output of the buffer 11 whenthe clock pulse CP1 is generated is sent to the arithmetic operationunit 50b. At this time, the output P of the parity calculator 17 is "0"(FIG. 8j) and the arithmetic operation unit 50b is at the subtractivemode (FIG. 8k). At this time, since the register 50c is storing "000,"the record word charge information is applied with a negative sign thusbecoming -2, which is supplied to the shift register 50c. This shiftregister stores -2 at time t₅₃ when the clock pulse CP4 shown in FIG. 4fis generated. Thus, -2 is outputted as the output of the register 50c(see FIG. 8l). At this time, the output C is "1" (FIG. 8m). At thistime, although the exclusive-OR gate circuit 13b1 produces an output"1", the flip-flop circuit 50d is not in a state of receiving thisoutput "1".

Then at time t₅₄ the clock pulse CP2 (FIG. 8g) which sequentially shiftsthe content of the shift register 15 is generated, while at the sametime, the clock pulse CP3 (see FIG. 8i) that enables the flip-flopcircuit of the parity calculator 17 is also generated. Upon receival ofthis clock pulse, the parity calculator 17 stores a parity information"1" sent out from ROM 51 when it receives the output of buffer 11 whenthe clock pulse CP1 is generated thereby producing an output P of "1"(see FIG. 8j). When the output P becomes "1", the mode of the arithmeticoperation unit 51 is transferred to the addition mode. Since at thistime the exclusive-OR gate circuit 13b1 is supplied with outputs P and C(both "0") the AND gate circuits 17_(b3) and 17_(b4) would not beenabled thus sending out "0". At this state, the clock pulse CP5 issupplied to the flip-flop circuit 50d so that it is reset to send a Qoutput of "0" to the ROM 51.

When the next data word "010" is applied to the buffer 11 this data wordis sent to the ROM 51 to act as a lower order address bit of the ROM asshown in FIG. 8c. At this time, since the flip-flop circuit 50d issending out "0" as its Q output, the address input to the ROM 51 becomes"0010". At this time the output of ROM 51 becomes "1101/1/0" accordingto Table II. The operation sending and storing the record word "1101" inthe shift register 15 is the same as that described above. The paritycalculator 17 is sending out a output P of "1", but since the recordword charge information is "0" the output of the register 50c appears onthe outside of the arithmetic operation unit 50b as it is and writtenagain into the register 50c when the clock pulse CP4 is generated attime t₅₆ (see FIG. 8l).

Thereafter, although the parity calculator 17 receives a clock pulse CP3at time t₅₇, since the J-K type flip-flop circuit 17a receive the sameinput "1" as before, its state is changed to produce an output P of "0".Under this state, since the output C of the register 50c is "1" and theoutput P of the flip-flop circuit 17a is "0" the exclusive-OR gatecircuit 13_(b1) produces an output "1" and then "1" is stored in theflip-flop circuit 50d by the clock pulse CP5 supplied at a time of t₅₈.As a consequence, when the next data word "101" is written into thebuffer 11, data "1101" would be supplied to the ROM 51 as its addressinput. The succeeding operation is the same as that described above.

With this construction it is possible to use the ROM 51 as a portion ofthe charge calculator.

As can be noted from the comparison of FIGS. 4 and 8, the time duringwhich the necessary ROM address has to be maintained is longer in FIG.8, it is the configuration by FIG. 8 that can realize the higher datatransfer speed and higher speed of writing.

It should be understood that the invention is not limited to thespecific embodiments described above and that various kinds ofapplications, and modifications can be made.

For example, the conversion table shown in FIG. 1 and the conversionformats shown in Table I and II are were illustrative and the number mof the bits of a data word and the number n (n>m) of the bits of arecord word can be determined arbitrarily. Furthermore, the number ofdata words corresponding to 1 to 2 can be selected arbitrarily so longas the construction is possible.

With the construction described above, it is possible to eliminate a DCcomponent of the recording current by converting a data word obtained bypartitioning an original information bit sequence at every m bits into nbit record bit (n>m). The magnetic polarity of only a record bit "1" isinverted and then recorded on a magnetic medium and the presence andabsence of the magnetic polarity inversion is converted into a detecteddigit (3 values) with a class 1 partial response system. Each n digitsare converted into a data word without using other digits. Accordingly,it is possible to realize higher linear bit density than the prior artapparatus. Furthermore, as the inter-symbol interference is permitted byapplying a partial response system at the time of reproduction, it ispossible to narrow the spacing between magnetic polarity inversion, thusenabling higher linear bit density. For example, when compared with aprior art DC component free encoding system disclosed in U.S. Pat. No.4,037,335 it is possible to obtain about 1.5 times of the linear bitdensity. Further, when reproducing a data word as it is not necessary touse digits other than a detection digit corresponding to that data word,it is possible to prevent propagation of the error produced at the timeof reproduction successively to succeeding bits without the necessity ofusing a precoder for preventing error propagation as disclosed in U.S.Pat. No. 3,648,265. In contrast, according to this invention as zero DCencoding is used, it is not necessary to use such precoder.

What is claimed is:
 1. A method of magnetically recording and reproducing a digital informations comprising the steps of:preparing a conversion table in which data words each comprising a plurality of (m) bits correspond to respective record words each having n bits (n>m) and in which an integrated value of NRZI recording current becomes zero, or two record words each including n bits and in which the integrated value of NRZI recording current is not zero and polarities of said two record words are opposite; partitioning an original information bit sequence into data words at every m bits; converting the data words into record words when the former correspond to record words in said conversion table; when one of said data words corresponds to two record words in said conversion table, converting one of said record words into a record word such that, in accordance with the integrated value of the NIRZI recording current up to a conversion point, an absolute value of said integrated value would decrease; recording a record word sequence obtained by said conversion on a magnetic medium as a magnetic polarity inversion sequence

    a.sub.o, a.sub.1, a.sub.2, . . . a.sub.i

where ai represents by 1 or -1 a magnetic inversion in which two N poles oppose each other or two S poles oppose each other, and by 0 a magnetic polarity noninversion and i represents a position in said magnetic polarity inversion sequence; reading said magnetic polarity inversion sequence out of said magnetic medium converting read out informations into a 3 valued detected digit sequence of class 1 partial response type expressed by

    b.sub.o, b.sub.1, b.sub.2, . . . b.sub.j . . .

where b_(j) =a_(j-l) +a_(j) converting said detected digit sequence into m bit data words at every n digits; and reproducing the m bit data words.
 2. The apparatus for recording and reproducing digital informations comprising:an encoder provided with a conversion table according to which m bit data words are converted into n bits (n>m) record words by said data words acting as address inputs; an n bit shift register which in parallel stores, at a first timing, said n bit record words outputted from said encoder; an NRZI recording current modulator for producing an NRZI recording current in accordance with serially read out record words from said shift register at a second timing; a head connected to receive outputs of said NRZI recording current modulator for recording digital informations on a recording medium; means for detecting whether an integrated value of the NRZI current is zero or not; and means for generating a control signal which selects a record word to be converted by said encoder according to a data word supplied at the next time according to an output of said detecting means and integrated value of the NRZI recording current up to a conversion point; said conversion table of said encoder including a first portion in which respective data words are converted into one record word wherein the integrated value of the NRZI recording current becomes zero, and a second portion in which respective data words are converted into two record words wherein the integrated value of the NRZI recording current is not zero and the record words have different polarities, and said control signal generating means sending to said encoder a control signal which selects a record word having a sign which makes small the integrated value of the NRZI recording current up to a conversion point when said detecting means determines that the integrated value of said NRZI recording current does not become zero.
 3. The apparatus according to claim 2 wherein said encoder is constituted by a ROM.
 4. The apparatus according to claim 2 wherein said detecting means performs a detection operation according to an output of said shift register.
 5. The apparatus according to claim 2 wherein said encoder comprises a J-K flip-flop circuit.
 6. The apparatus according to claim 2 wherein said control signal generating means comprise an up-down counter, a J-K flip-flop circuit supplied with an output of said shift register, a gate circuit for controlling up and down counts of said up-down counter under control of an output of said J-K flip-flop circuit, an exclusive OR gate circuit supplied with a most significant bit output of said up-down counter, and an output of said detecting means, and means for supplying an output of said exclusive OR gate circuit to said encoder.
 7. The apparatus according to claim 6 wherein the output of said exclusive-OR gate circuit designated said conversion table in combination with said data word.
 8. The apparatus according to claim 2 which further comprises a buffer which temporarily stores said data word at a third timing before said data word is sent to said encoder.
 9. The apparatus according to claim 2 wherein said conversion table stores record words to be converted from data words, a control information necessary to determine whether the integrated value of the NRZI recording current formed according to the record words is zero or not, and a charge information when the integrated value of the NRZI current formed according to the record words is not zero, wherein said detecting means operates in response to the control information necessary to determine whether the integrated value of the NRZI recording current is zero or not, and wherein said control signal generating means operates according to said charge information.
 10. The apparatus according to claim 9 wherein said control signal generating means comprises an arithmetic operation unit supplied with an output of said encoder, a register for storing an output of said arithmetic operation unit at a third timing, an exclusive-OR gate circuit supplied with a portion of an output of said register and an output of said detecting means, and a flip-flop circuit for receiving an output of said exclusive-OR gate circuit at a fourth timing, said arithmetic operation unit adding or subtracting said two outputs applied thereto in accordance an output of said register and under control of an output of said detecting means and an output of said flip-flop circuit being sent to said encoder.
 11. The apparatus according to claim 1 which further comprises reproducing apparatus including a reproducing head which reproduces digital informations recorded on said recording medium with a NRZI system, means for converting signals reproduced by said reproducing head into 3 valued detected digit sequence of a class 1 partial response type and means for converting said detected digit sequence into m bit data words at every n digits.
 12. The apparatus according to claim 11 wherein said converting means comprises amplitude detectors which convert said reproduced signals into said 3 valued detected digit sequence depending upon a judgment as to whether amplitude values of the reproduced signals are larger or smaller than a reference value set around a zero level, an inversion detector for detecting whether the reproduced signals have been inverted or not, and means for sending an output of said amplitude detector to said converting means.
 13. The apparatus according to claim 11 wherein said converting means comprises two shift registers which serially receive and store outputs of respective detectors at a third timing and in parallel send out stored outputs, and a decoder supplied with outputs of said two shift registers for forming data words with a conversion table opposite to said first mentioned conversion table. 